error
39_Fused1DTemporalConvolution.py
started
2026-05-02T21:45:20Z
reference PyTorch source (the prompt the agent sees)
import torch
import torch.nn as nn
import torch.nn.functional as F
# Default ModelNew is PyTorch-only. run_and_check: use check_kernel=False with backend=cuda
# until the candidate file contains a real CUDA kernel (see kernel_static_checker).
class Model(nn.Module):
"""
**Fused depthwise–pointwise 1D temporal convolution** on ``(B, C, T)`` sequences.
Fuses a **temporal depthwise** ``k``-tap conv (per-channel along time) with
**SiLU** and a **pointwise** ``1×1`` mix—standard in temporal encoders for
proprio, audio, or token-wise time series in robotics / VLA backbones.
Padding uses dilated effective radius so length is unchanged for odd
``kernel_size``.
"""
def __init__(
self,
in_channels: int,
out_channels: int,
kernel_size: int,
dilation: int = 1,
):
super().__init__()
assert kernel_size % 2 == 1, "odd kernel_size keeps T unchanged with symmetric padding"
assert dilation >= 1
self.padding = ((kernel_size - 1) * dilation) // 2
self.dw = nn.Conv1d(
in_channels,
in_channels,
kernel_size,
padding=self.padding,
dilation=dilation,
groups=in_channels,
bias=False,
)
self.pw = nn.Conv1d(in_channels, out_channels, kernel_size=1, bias=False)
def forward(self, x: torch.Tensor) -> torch.Tensor:
"""
Args:
x: (B, C_in, T) temporal features.
Returns:
(B, C_out, T)
"""
x = self.dw(x)
x = F.silu(x)
return self.pw(x)
class ModelNew(nn.Module):
"""KernelBench candidate entry point; default delegates to ``Model``."""
def __init__(
self,
in_channels: int,
out_channels: int,
kernel_size: int,
dilation: int = 1,
):
super().__init__()
self._impl = Model(in_channels, out_channels, kernel_size, dilation=dilation)
def forward(self, x: torch.Tensor) -> torch.Tensor:
return self._impl(x)
batch_size = 16
in_channels = 128
out_channels = 128
kernel_size = 5
dilation = 2
seq_len = 2048
def get_inputs():
p = popcorn_pri
x = torch.randn(p.jitter_int(batch_size), in_channels, p.jitter_int(seq_len))
return [x]
def get_init_inputs():
return [in_channels, out_channels, kernel_size, dilation]
turn 015.5s turn · 15.5s LLM · 0.0s tools
reasoning
**Considering tile sizes**
I’m looking into the tile size options here. I need a tile of 16x32 but maybe I should block it down to 16x16 outputs instead. It seems like I could compute each output using 256 threads, which means I’d need to loop through the C tile. Let's explore how this setup might work in practice and if it really fits my needs. I want to ensure everything aligns smoothly!
call → get_gpu_specs
callget_gpu_specs
{}
result ← get_gpu_specs (ok)
okget_gpu_specs
GPU specs for NVIDIA H100 80GB HBM3:
total memory (runtime): 79.1 GB
spec entry: H100
GPU Architecture: Hopper
GPU Memory: 80GB
Memory Bandwidth: 3.35 TB/s
FP64 TFLOPS: 34
FP64 Tensor Core TFLOPS: 67
FP32 TFLOPS: 67
TF32 Tensor Core TFLOPS: 989 with sparsity
BFLOAT16 Tensore Core TFLOPS: 1979 with sparsity
FP16 Tensor Core TFLOPS: 1979 with sparsity
FP8 Tensor Core TFLOPS: 3958 with sparsity
INT8 Tensor Core TOPS: 3958 with sparsity
Register File Size: 64K 32-bit registers per SM
Maximum number of registers per thread: 255
Maximum number of thread blocks per SM: 32
Shared memory capacity per SM: 228 KB
Maximum shared memory per thread block: 227 KB
turn 16760.9s turn · 6760.9s LLM · 0.0s tools
feedbackLLM call failed: _WorkItemTimeout: work item exceeded soft timeout budget