gpt-5.5-priority · original · l123_single_gpt
correct 86_conv_depthwise_separable_2D.py
model
gpt-5.5-priority
turns / max
1 / 1
tool calls
1
tokens (total)
0
wall clock
—
truncated
no
backend
cuda fp32
variant
original
runtime
3.07 μs
ref runtime
3.81 μs
speedup
1.24x
started
2026-05-05T00:56:52Z
timingkernelbench.timing
kernel runtime
3.07 μs
ref runtime
3.81 μs
speedup
1.24x
kernel mean / median / std
3.07 / — / 0.31 μs
ref mean / median / std
3.81 / — / 1.45 μs
numerical precisioneval_kernel_against_ref
max abs error
0.00
mean abs error
0.00
max rel error
0.00
mean rel error
0.00
gpu memoryextended_metrics.measure_memory
kernel peak
4129.07 MB
ref peak
4129.07 MB
kernel / ref
1.00x
kernel launches / fusiontorch.profiler
kernel launches
5
ref launches
10
fusion ratio (ref / kernel)
2.00x
total cuda time
5407 μs
energyNVML (pynvml)
kernel mJ / run
480.88
ref mJ / run
1923.12
ratio (ref / kernel)
4.00x
avg power
159.13 W
ref avg power
527.09 W
SOL (speed-of-light)nsight_hardware_counters
SOL score (0–1)
1.000
dram util %
100.0%
compute util %
13.2%
bottleneck
memory-bound
dominant pipe
tensor-core
arithmetic intensity
—
ridge point
295.22
roofline / occupancynsight_hardware_counters
dram bandwidth
3909.00 GB/s
dram util %
100.0%
fp32 tflops
—
fp32 util %
—
fp16 tflops
—
occupancy %
110.7%
bottleneck
memory-bound
dominant pipe %
13.2%
arithmetic intensity
—
ridge point
295.22
L1 hit %
—
L2 hit %
136.1%
ld sectors / req
1.63
st sectors / req
—
regs / thread
199
smem / block
236032 B
block size
896
peak bw
3350.00 GB/s
peak fp32 tflops
67.00
peak fp16 tflops
1979.00
warp stalls (top 5)nsight
long_scoreboard
1440.6%
mio_throttle
229.3%
short_scoreboard
198.1%
reference PyTorch source (the prompt the agent sees)
import torch
import torch.nn as nn

class Model(nn.Module):
    """
    Performs a depthwise-separable 2D convolution operation.

    Args:
        in_channels (int): Number of channels in the input tensor.
        out_channels (int): Number of channels produced by the convolution.
        kernel_size (int): Size of the convolution kernel.
        stride (int, optional): Stride of the convolution. Defaults to 1.
        padding (int, optional): Padding applied to the input. Defaults to 0.
        dilation (int, optional): Spacing between kernel elements. Defaults to 1.
        bias (bool, optional): If `True`, adds a learnable bias to the output. Defaults to `False`.
    """
    def __init__(self, in_channels: int, out_channels: int, kernel_size: int, stride: int = 1, padding: int = 0, dilation: int = 1, bias: bool = False):
        super(Model, self).__init__()
        self.depthwise = nn.Conv2d(in_channels, in_channels, kernel_size, stride=stride, padding=padding, dilation=dilation, groups=in_channels, bias=bias)
        self.pointwise = nn.Conv2d(in_channels, out_channels, kernel_size=1, bias=bias)
        
    def forward(self, x: torch.Tensor) -> torch.Tensor:
        """
        Performs the depthwise-separable 2D convolution.

        Args:
            x (torch.Tensor): Input tensor of shape (batch_size, in_channels, height, width).

        Returns:
            torch.Tensor: Output tensor of shape (batch_size, out_channels, height_out, width_out).
        """
        x = self.depthwise(x)
        x = self.pointwise(x)
        return x

# Test code
batch_size = 16
in_channels = 64
out_channels = 128
kernel_size = 3
width = 512
height = 512
stride = 1
padding = 1
dilation = 1

def get_inputs():
    x = torch.rand(batch_size, in_channels, height, width)
    return [x]

def get_init_inputs():
    return [in_channels, out_channels, kernel_size, stride, padding, dilation]
turn 0 · FINAL · 1 tool call(s) · 68.5s turn · 68.5s LLM · 9,851 chars (click to expand)
turn 068.5s turn · 68.5s LLM · 0.0s tools · FINAL
call → submit_kernel
callsubmit_kernel { "kernel_code": "import torch\nimport torch.nn as nn\nimport torch.nn.functional as F\nfrom torch.utils.cpp_extension import load_inline\n\n_cpp_src = r\"\"\"\n#include <torch/extension.h>\n\ntorch::Tensor depthwise_cuda(torch::Tensor x, torch::Tensor w, torch::Tensor bias, bool has_bias,\n int64_t stride, int64_t padding, int64_t dilation);\n\"\"\"\n\n_cuda_src = r\"\"\"\n#include <torch/extension.h>\n#include <ATen/cuda/CUDAContext.h>\n#include <c10/cuda/CUDAGuard.h>\n\n#define CHECK_CUDA(x) TORCH_CHECK(x.is_cuda(), #x \" must be a CUDA tensor\")\n#define CHECK_CONTIGUOUS(x) TORCH_CHECK(x.is_contiguous(), #x \" must be contiguous\")\n\n// Optimized path for the benchmark case: k=3, stride=1, padding=1, dilation=1.\n// One CTA computes a 32x16 spatial tile for one (N,C) plane. The input tile\n// including halo is staged in shared memory, reducing the 3x3 depthwise pass to\n// about one global load per output element.\n__global__ __launch_bounds__(512, 2)\nvoid dw3x3s1p1_kernel(const float* __restrict__ x,\n const float* __restrict__ w,\n const float* __restrict__ b,\n float* __restrict__ y,\n int NC, int H, int W) {\n constexpr int TW = 32;\n constexpr int TH = 16;\n constexpr int SW = TW + 2;\n constexpr int SH = TH + 2;\n __shared__ float sh[SH * SW];\n\n const int tx = threadIdx.x;\n const int ty = threadIdx.y;\n const int tid = ty * blockDim.x + tx;\n const int z = blockIdx.z; // n*C + c\n const int c = z % NC; // actually C is passed as NC? see below no\n}\n\n__global__ __launch_bounds__(512, 2)\nvoid dw3x3s1p1_kernel2(const float* __restrict__ x,\n const float* __restrict__ w,\n const float* __restrict__ b,\n float* __restrict__ y,\n int C, int H, int W) {\n constexpr int TW = 32;\n constexpr int TH = 16;\n constexpr int SW = TW + 2;\n constexpr int SH = TH + 2;\n __shared__ float sh[SH * SW];\n\n const int tx = threadIdx.x;\n const int ty = threadIdx.y;\n const int tid = ty * 32 + tx;\n const int z = blockIdx.z; // n*C + c\n const int c = z % C;\n const int ox0 = blockIdx.x * TW;\n const int oy0 = blockIdx.y * TH;\n\n // Cooperative load of the 34x18 tile including zero-padding halo.\n #pragma unroll\n for (int i = 0; i < SH * SW; i += 512) {\n int j = i + tid;\n if (j < SH * SW) {\n int sy = j / SW;\n int sx = j - sy * SW;\n int iy = oy0 + sy - 1;\n int ix = ox0 + sx - 1;\n float v = 0.0f;\n if ((unsigned)iy < (unsigned)H && (unsigned)ix < (unsigned)W) {\n v = x[((long long)z * H + iy) * W + ix];\n }\n sh[j] = v;\n }\n }\n __syncthreads();\n\n const int ox = ox0 + tx;\n const int oy = oy0 + ty;\n if (ox < W && oy < H) {\n const float* __restrict__ wc = w + c * 9;\n float acc = 0.0f;\n acc = fmaf(wc[0], sh[(ty + 0) * SW + tx + 0], acc);\n acc = fmaf(wc[1], sh[(ty + 0) * SW + tx + 1], acc);\n acc = fmaf(wc[2], sh[(ty + 0) * SW + tx + 2], acc);\n acc = fmaf(wc[3], sh[(ty + 1) * SW + tx + 0], acc);\n acc = fmaf(wc[4], sh[(ty + 1) * SW + tx + 1], acc);\n acc = fmaf(wc[5], sh[(ty + 1) * SW + tx + 2], acc);\n acc = fmaf(wc[6], sh[(ty + 2) * SW + tx + 0], acc);\n acc = fmaf(wc[7], sh[(ty + 2) * SW + tx + 1], acc);\n acc = fmaf(wc[8], sh[(ty + 2) * SW + tx + 2], acc);\n if (b != nullptr) acc += b[c];\n y[((long long)z * H + oy) * W + ox] = acc;\n }\n}\n\n__global__ void dw_generic_kernel(const float* __restrict__ x,\n const float* __restrict__ w,\n const float* __restrict__ b,\n float* __restrict__ y,\n int N, int C, int H, int W, int K,\n int Ho, int Wo, int stride, int pad, int dil) {\n long long total = (long long)N * C * Ho * Wo;\n long long idx = (long long)blockIdx.x * blockDim.x + threadIdx.x;\n long long step = (long long)blockDim.x * gridDim.x;\n for (; idx < total; idx += step) {\n int ow = idx % Wo;\n long long t = idx / Wo;\n int oh = t % Ho;\n t /= Ho;\n int c = t % C;\n int n = t / C;\n float acc = 0.0f;\n int base_y = oh * stride - pad;\n int base_x = ow * stride - pad;\n const float* __restrict__ wc = w + (long long)c * K * K;\n for (int ky = 0; ky < K; ++ky) {\n int iy = base_y + ky * dil;\n if ((unsigned)iy >= (unsigned)H) continue;\n for (int kx = 0; kx < K; ++kx) {\n int ix = base_x + kx * dil;\n if ((unsigned)ix < (unsigned)W) {\n float xv = x[((long long)n * C + c) * H * W + (long long)iy * W + ix];\n acc = fmaf(wc[ky * K + kx], xv, acc);\n }\n }\n }\n if (b != nullptr) acc += b[c];\n y[idx] = acc;\n }\n}\n\ntorch::Tensor depthwise_cuda(torch::Tensor x, torch::Tensor w, torch::Tensor bias, bool has_bias,\n int64_t stride, int64_t padding, int64_t dilation) {\n CHECK_CUDA(x); CHECK_CUDA(w);\n CHECK_CONTIGUOUS(x); CHECK_CONTIGUOUS(w);\n const at::cuda::OptionalCUDAGuard device_guard(device_of(x));\n\n const int N = (int)x.size(0);\n const int C = (int)x.size(1);\n const int H = (int)x.size(2);\n const int W = (int)x.size(3);\n const int K = (int)w.size(2);\n const int Ho = (H + 2 * (int)padding - (int)dilation * (K - 1) - 1) / (int)stride + 1;\n const int Wo = (W + 2 * (int)padding - (int)dilation * (K - 1) - 1) / (int)stride + 1;\n\n auto y = torch::empty({N, C, Ho, Wo}, x.options());\n const float* bp = has_bias ? bias.data_ptr<float>() : nullptr;\n cudaStream_t stream = at::cuda::getCurrentCUDAStream();\n\n if (K == 3 && stride == 1 && padding == 1 && dilation == 1 && Ho == H && Wo == W) {\n dim3 block(32, 16, 1);\n dim3 grid((W + 31) / 32, (H + 15) / 16, N * C);\n dw3x3s1p1_kernel2<<<grid, block, 0, stream>>>(x.data_ptr<float>(), w.data_ptr<float>(), bp,\n y.data_ptr<float>(), C, H, W);\n } else {\n int threads = 256;\n int blocks = (int)std::min<long long>(65535LL, ((long long)N * C * Ho * Wo + threads - 1) / threads);\n dw_generic_kernel<<<blocks, threads, 0, stream>>>(x.data_ptr<float>(), w.data_ptr<float>(), bp,\n y.data_ptr<float>(), N, C, H, W, K, Ho, Wo,\n (int)stride, (int)padding, (int)dilation);\n }\n return y;\n}\n\"\"\"\n\n_ext = load_inline(\n name=\"dw_sep_depthwise_ext_v1\",\n cpp_sources=_cpp_src,\n cuda_sources=_cuda_src,\n functions=[\"depthwise_cuda\"],\n extra_cflags=[\"-O3\"],\n extra_cuda_cflags=[\"-O3\", \"--use_fast_math\"],\n verbose=False,\n)\n\nclass ModelNew(nn.Module):\n def __init__(self, in_channels: int, out_channels: int, kernel_size: int,\n stride: int = 1, padding: int = 0, dilation: int = 1, bias: bool = False):\n super(ModelNew, self).__init__()\n self.depthwise = nn.Conv2d(in_channels, in_channels, kernel_size, stride=stride,\n padding=padding, dilation=dilation, groups=in_channels, bias=bias)\n self.pointwise = nn.Conv2d(in_channels, out_channels, kernel_size=1, bias=bias)\n self.stride = int(stride)\n self.padding = int(padding)\n self.dilation = int(dilation)\n self.register_buffer(\"_empty_bias\", torch.empty(0), persistent=False)\n\n def forward(self, x: torch.Tensor) -> torch.Tensor:\n # Custom CUDA depthwise pass, followed by the highly optimized library 1x1 convolution.\n db = self.depthwise.bias\n if db is None:\n dw = _ext.depthwise_cuda(x, self.depthwise.weight, self._empty_bias, False,\n self.stride, self.padding, self.dilation)\n else:\n dw = _ext.depthwise_cuda(x, self.depthwise.weight, db, True,\n self.stride, self.padding, self.dilation)\n return F.conv2d(dw, self.pointwise.weight, self.pointwise.bias, stride=1, padding=0, dilation=1, groups=1)\n" }
result ← submit_kernel (ok)
oksubmit_kernel submit_kernel PASSED: (5 / 5) correctness trials all passed. Kernel runtime: 3.07 μs Runtime stats: mean=3.07μs median=?μs std=0.31μs Numerical precision: max_abs_err=0.00e+00 mean_abs_err=0.00e+00 max_rel_err=0.00e+00 Memory: 4129.07 MB peak (ref: 4129.07 MB, ratio: 1.0x) Kernel launches: 5 (ref: 10, fusion ratio: 2.0) Energy: 480.88 mJ/run (ref: 1923.12 mJ, ratio: 3.9992x) SOL score: 1.0
final submitted kernel (203 lines, 8,391 chars) — full source, untruncated
import torch
import torch.nn as nn
import torch.nn.functional as F
from torch.utils.cpp_extension import load_inline

_cpp_src = r"""
#include <torch/extension.h>

torch::Tensor depthwise_cuda(torch::Tensor x, torch::Tensor w, torch::Tensor bias, bool has_bias,
                             int64_t stride, int64_t padding, int64_t dilation);
"""

_cuda_src = r"""
#include <torch/extension.h>
#include <ATen/cuda/CUDAContext.h>
#include <c10/cuda/CUDAGuard.h>

#define CHECK_CUDA(x) TORCH_CHECK(x.is_cuda(), #x " must be a CUDA tensor")
#define CHECK_CONTIGUOUS(x) TORCH_CHECK(x.is_contiguous(), #x " must be contiguous")

// Optimized path for the benchmark case: k=3, stride=1, padding=1, dilation=1.
// One CTA computes a 32x16 spatial tile for one (N,C) plane.  The input tile
// including halo is staged in shared memory, reducing the 3x3 depthwise pass to
// about one global load per output element.
__global__ __launch_bounds__(512, 2)
void dw3x3s1p1_kernel(const float* __restrict__ x,
                      const float* __restrict__ w,
                      const float* __restrict__ b,
                      float* __restrict__ y,
                      int NC, int H, int W) {
    constexpr int TW = 32;
    constexpr int TH = 16;
    constexpr int SW = TW + 2;
    constexpr int SH = TH + 2;
    __shared__ float sh[SH * SW];

    const int tx = threadIdx.x;
    const int ty = threadIdx.y;
    const int tid = ty * blockDim.x + tx;
    const int z = blockIdx.z;       // n*C + c
    const int c = z % NC;           // actually C is passed as NC? see below no
}

__global__ __launch_bounds__(512, 2)
void dw3x3s1p1_kernel2(const float* __restrict__ x,
                       const float* __restrict__ w,
                       const float* __restrict__ b,
                       float* __restrict__ y,
                       int C, int H, int W) {
    constexpr int TW = 32;
    constexpr int TH = 16;
    constexpr int SW = TW + 2;
    constexpr int SH = TH + 2;
    __shared__ float sh[SH * SW];

    const int tx = threadIdx.x;
    const int ty = threadIdx.y;
    const int tid = ty * 32 + tx;
    const int z = blockIdx.z;       // n*C + c
    const int c = z % C;
    const int ox0 = blockIdx.x * TW;
    const int oy0 = blockIdx.y * TH;

    // Cooperative load of the 34x18 tile including zero-padding halo.
    #pragma unroll
    for (int i = 0; i < SH * SW; i += 512) {
        int j = i + tid;
        if (j < SH * SW) {
            int sy = j / SW;
            int sx = j - sy * SW;
            int iy = oy0 + sy - 1;
            int ix = ox0 + sx - 1;
            float v = 0.0f;
            if ((unsigned)iy < (unsigned)H && (unsigned)ix < (unsigned)W) {
                v = x[((long long)z * H + iy) * W + ix];
            }
            sh[j] = v;
        }
    }
    __syncthreads();

    const int ox = ox0 + tx;
    const int oy = oy0 + ty;
    if (ox < W && oy < H) {
        const float* __restrict__ wc = w + c * 9;
        float acc = 0.0f;
        acc = fmaf(wc[0], sh[(ty + 0) * SW + tx + 0], acc);
        acc = fmaf(wc[1], sh[(ty + 0) * SW + tx + 1], acc);
        acc = fmaf(wc[2], sh[(ty + 0) * SW + tx + 2], acc);
        acc = fmaf(wc[3], sh[(ty + 1) * SW + tx + 0], acc);
        acc = fmaf(wc[4], sh[(ty + 1) * SW + tx + 1], acc);
        acc = fmaf(wc[5], sh[(ty + 1) * SW + tx + 2], acc);
        acc = fmaf(wc[6], sh[(ty + 2) * SW + tx + 0], acc);
        acc = fmaf(wc[7], sh[(ty + 2) * SW + tx + 1], acc);
        acc = fmaf(wc[8], sh[(ty + 2) * SW + tx + 2], acc);
        if (b != nullptr) acc += b[c];
        y[((long long)z * H + oy) * W + ox] = acc;
    }
}

__global__ void dw_generic_kernel(const float* __restrict__ x,
                                  const float* __restrict__ w,
                                  const float* __restrict__ b,
                                  float* __restrict__ y,
                                  int N, int C, int H, int W, int K,
                                  int Ho, int Wo, int stride, int pad, int dil) {
    long long total = (long long)N * C * Ho * Wo;
    long long idx = (long long)blockIdx.x * blockDim.x + threadIdx.x;
    long long step = (long long)blockDim.x * gridDim.x;
    for (; idx < total; idx += step) {
        int ow = idx % Wo;
        long long t = idx / Wo;
        int oh = t % Ho;
        t /= Ho;
        int c = t % C;
        int n = t / C;
        float acc = 0.0f;
        int base_y = oh * stride - pad;
        int base_x = ow * stride - pad;
        const float* __restrict__ wc = w + (long long)c * K * K;
        for (int ky = 0; ky < K; ++ky) {
            int iy = base_y + ky * dil;
            if ((unsigned)iy >= (unsigned)H) continue;
            for (int kx = 0; kx < K; ++kx) {
                int ix = base_x + kx * dil;
                if ((unsigned)ix < (unsigned)W) {
                    float xv = x[((long long)n * C + c) * H * W + (long long)iy * W + ix];
                    acc = fmaf(wc[ky * K + kx], xv, acc);
                }
            }
        }
        if (b != nullptr) acc += b[c];
        y[idx] = acc;
    }
}

torch::Tensor depthwise_cuda(torch::Tensor x, torch::Tensor w, torch::Tensor bias, bool has_bias,
                             int64_t stride, int64_t padding, int64_t dilation) {
    CHECK_CUDA(x); CHECK_CUDA(w);
    CHECK_CONTIGUOUS(x); CHECK_CONTIGUOUS(w);
    const at::cuda::OptionalCUDAGuard device_guard(device_of(x));

    const int N = (int)x.size(0);
    const int C = (int)x.size(1);
    const int H = (int)x.size(2);
    const int W = (int)x.size(3);
    const int K = (int)w.size(2);
    const int Ho = (H + 2 * (int)padding - (int)dilation * (K - 1) - 1) / (int)stride + 1;
    const int Wo = (W + 2 * (int)padding - (int)dilation * (K - 1) - 1) / (int)stride + 1;

    auto y = torch::empty({N, C, Ho, Wo}, x.options());
    const float* bp = has_bias ? bias.data_ptr<float>() : nullptr;
    cudaStream_t stream = at::cuda::getCurrentCUDAStream();

    if (K == 3 && stride == 1 && padding == 1 && dilation == 1 && Ho == H && Wo == W) {
        dim3 block(32, 16, 1);
        dim3 grid((W + 31) / 32, (H + 15) / 16, N * C);
        dw3x3s1p1_kernel2<<<grid, block, 0, stream>>>(x.data_ptr<float>(), w.data_ptr<float>(), bp,
                                                       y.data_ptr<float>(), C, H, W);
    } else {
        int threads = 256;
        int blocks = (int)std::min<long long>(65535LL, ((long long)N * C * Ho * Wo + threads - 1) / threads);
        dw_generic_kernel<<<blocks, threads, 0, stream>>>(x.data_ptr<float>(), w.data_ptr<float>(), bp,
                                                          y.data_ptr<float>(), N, C, H, W, K, Ho, Wo,
                                                          (int)stride, (int)padding, (int)dilation);
    }
    return y;
}
"""

_ext = load_inline(
    name="dw_sep_depthwise_ext_v1",
    cpp_sources=_cpp_src,
    cuda_sources=_cuda_src,
    functions=["depthwise_cuda"],
    extra_cflags=["-O3"],
    extra_cuda_cflags=["-O3", "--use_fast_math"],
    verbose=False,
)

class ModelNew(nn.Module):
    def __init__(self, in_channels: int, out_channels: int, kernel_size: int,
                 stride: int = 1, padding: int = 0, dilation: int = 1, bias: bool = False):
        super(ModelNew, self).__init__()
        self.depthwise = nn.Conv2d(in_channels, in_channels, kernel_size, stride=stride,
                                   padding=padding, dilation=dilation, groups=in_channels, bias=bias)
        self.pointwise = nn.Conv2d(in_channels, out_channels, kernel_size=1, bias=bias)
        self.stride = int(stride)
        self.padding = int(padding)
        self.dilation = int(dilation)
        self.register_buffer("_empty_bias", torch.empty(0), persistent=False)

    def forward(self, x: torch.Tensor) -> torch.Tensor:
        # Custom CUDA depthwise pass, followed by the highly optimized library 1x1 convolution.
        db = self.depthwise.bias
        if db is None:
            dw = _ext.depthwise_cuda(x, self.depthwise.weight, self._empty_bias, False,
                                     self.stride, self.padding, self.dilation)
        else:
            dw = _ext.depthwise_cuda(x, self.depthwise.weight, db, True,
                                     self.stride, self.padding, self.dilation)
        return F.conv2d(dw, self.pointwise.weight, self.pointwise.bias, stride=1, padding=0, dilation=1, groups=1)